This invention is related to generating a lithographic photomask and, more particularly, to an algorithm for integrating embedded DRAMs with silicon-on-insulator technology by patterning the semiconductor wafer into bulk areas for embedded DRAM processing and silicon-on-insulator areas for logic circuit processing.
As microprocessor designs approach the 0.18 xcexcm node and beyond, the two primary concerns that often arise are: the power consumption of the processor and the amount of on-chip memory (more commonly referred to as cache) that is required. Power consumption and the ensuing heat dissipation of the processor are a key area of interest, specially with regard to battery operated computing devices. A powerful way of reducing power consumption is to use silicon-on-insulator (SOI) wafers as substrates. As SOI wafers incorporate a buried oxide BOX) layer that is positioned underneath the active silicon region, the MOSFET junction capacitance (e.g., of source/drain diffusions) can be reduced significantly, as described, e.g., in U.S. Pat. No. 4,810,664 to Kamins et al. Thus, the voltages needed to drive devices can be lowered due to this capacitance reduction which, in turn, reduces the required power supply voltage (Vdd). The fact that SOI allows the construction of low Vt devices to maintain high logic performance is a clear advantage over that of traditional bulk silicon.
A second advantage that SOI wafers have over conventional bulk silicon wafers is the elimination of junction leakage between n-channel and p-channel devices. Ordinarily, isolated p-channel (for NFETS) and n-channel (for PFETS) xe2x80x9cwellsxe2x80x9d or xe2x80x9ctubsxe2x80x9dxe2x80x94formed by high energy ion implantation are used to isolate devices of opposite polarity. In SOI wafers, these devices are enclosed laterally by shallow trench isolation (STI) and below by the buried oxide layer (BOX). Hence, P or N isolated wells need not to be formed. By reducing or eliminating leakage between N and P type devices, one can also reduce the power necessary to maintain isolation.
The problem of on-chip memory is one that is much more compelling and harder to solve as the memory""s size is projected to grow substantially in future microprocessor designs. In many of today""s microprocessors, on-chip memory is filled exclusively with Static Random Access Memory (SRAM) and take up to 50-70% of the entire microprocessor""s real estate, depending on the amount of cache present on the chip. An SRAM cell is usually configured with a six transistor (6T) layout, typically four n-type Field Effect Transistors (NFETs) and two p-type FETS. The cell (or bit) size of the 6T layout is on the order of 4-6 mm2 for an 0.18 xcexcm logic generation. For subsequent logic generations, such as 0.13 xcexcm and 0.10 xcexcm, the cell size of the SRAM is projected to be of the order of 1 to 2 mm2. As the MPU requirement of on-chip memory increases from several hundred kilobits (Kb) to several tens of megabits (Mb), the size of SRAM memory blocks presents severe manufacturing constraints due to the resultant die size. The incorporation of on-chip SRAM cache is thus limited to the range of 1-10 Mb.
The on-chip memory area crisis can be solved by replacing some, if not all the SRAM caches with a high-performance DRAM cache, hereinafter referred to as an embedded DRAM or eDRAM in short. The eDRAM cell size is approximately 6 to 8 times smaller than an SRAM having the same lithographic dimensions. Thus, it may be advantageous to replace the SRAM cache with an eDRAM cache for the same memory space on a microprocessor chip, making it possible to place more eDRAM memory than SRAM memory. Since the processor has a larger memory space to temporarily store data, the effect on the processor and system is a much improved performance.
The process of combining eDRAM caches on SOI wafers is, however, non-trivial. The major concern with integrating a high-performance DRAM cache in SOI is the effect of the floating body of the DRAM pass transistors. More particularly, since MOS transistors have their terminal entirely on an insulator, the body region under the channel is electrically isolated from the substrate and, hence, it floats with respect to the potential. Due to the fact that the body of the pass transistor is totally enclosed by oxide, the natural accumulation of holes (p-type substrate) acts negatively to the array device by creating forward bias conditions which prevents off-state conditions. This potential leakage concern with SOI on the off-state characteristics of the array device is one of the reasons why SOI wafers are currently not used for DRAMs.
In order to circumvent the deleterious effect of SOI on DRAM array devices, it has been proposed that the SOI wafer be patterned such that bulk and SOI regions be part of the same wafer. This structure is characterized by having the bulk regions reserved for the DRAM cache while the SOI wafers are used for high performance logic circuits. Such a construction providing patterned SOI wafers is also described in the aforementioned U.S. Pat. No. 4,810,664 to Kamins et al., wherein bulk regions underneath transistors also provide BOX isolation underneath the source/drain diffusions.
As will be described hereinafter, the present invention makes use of a hardmask to intentionally shield areas of the silicon substrate from the oxygen implant that is used to form the SOI. (Note: this technique of forming SOI is commonly referred to separation by implantation of oxygen, or SIMOX in short). After implanting the silicon wafer with a high dose of oxygen (xe2x88x92E17/cm2) at high energies (i.e., xe2x88x9250 to 200 KeV), the wafer is annealed at extremely high temperatures (1300xc2x0 C.) to form the BOX layer and regrow single crystal silicon on top of it.
Within the context of the present invention, the BOX is formed underneath the source/drain diffusions only while leaving a bulk region for the body of the device. Herein, the body of the device is in direct contact with the substrate where it can be biased and which allows a path for holes to be xe2x80x9cdrainedxe2x80x9d into the substrate. However, this method has two potential drawbacks. First, the present invention is, most likely, limited to large transistor or gate channels on the order of 0.5 mm or greater. As the oxygen implant is usually performed at a high dose and at high energy, the lateral implantation length (commonly referred to as xe2x80x9cstragglexe2x80x9d) of the oxygen ions will naturally go underneath the hard mask. Due to the fact that the implant is carried out at high energies, the tolerance or control of the oxygen ions progressing laterally underneath the hard mask is extremely hard to control, thus limiting the use of this invention to transistor sizes greater than 0.5 mm. The second drawback of the invention is the alignment of the transistor or gate with the substrate contact created by the pattern SIMOX. If the transistor is misaligned with respect to the substrate contact, depending how far the substrate contact is from the device, one may still be faced with a floating body effect.
A more recent method of forming pattern SOI wafers using SIMOX is described in patent applications Ser. No. 09/197,693, now issued as U.S. Pat. No. 6,353,246, and Ser. No. 09/497,124, now abandoned, respectively filed on Nov. 23, 1998 and Feb. 2, 2000, entitled xe2x80x9cMethod for filtering dislocations in merged SOI/DRAM chipsxe2x80x9d. Therein is described a method of fabricating both SOI and non-SOI devices in a single semiconductor chip. Large areas of the silicon substrate are patterned so that the entire DRAM or eDRAM cache lies in the bulk region of the wafer while areas surrounding the chip lie in SOI. A hardmask process is used to pattern the large bulk areas for the DRAM or eDRAM cache while the majority of the wafer becomes SOI. Because there are bulk regions in a pattern SOI wafer for the eDRAM cache, these areas require isolated wells to be formed. In conventional bulk eDRAM CMOS, three wells are defined: an n-well onto which p-type FETs are built; a p-well onto which n-type FETs are built; and an array well (AW), which is a well with p-doping of a different concentration than the p-well, and which is used for the logic, control, sense amplifier circuits, and the like, along with all other n-type FET circuits on the semiconductor chip. The embedded DRAM array devices are all built in the way well.
In order to electrically isolate the embedded DRAM array well from adjacent wells, a band of n-doped silicon is designed to intersect the edges of the array well. This n-band surrounds the array well in a ring-like manner. Contact to the n-band is made through the n-well at the silicon surface and extends to the deep n-plate below the embedded DRAM array. Through the n-band contact, the n-band can be electrically biased.
To this effect, FIG. 1, shows a cross-section of the physical layout of a conventional embedded DRAM cell. Each cell has a trench storage capacitor. Access to the charge in the storage capacitor is controlled by biasing the NFET transistor gate and diffusion via the gate contact and diffusion contact, which is also referred to as the bit line contact. The storage capacitor is built on p-type substrate wafers. Since the transistor is an NFET, the transistor must also be fabricated onto p-doped silicon, (shown in FIG. 1 as the array well). To separate these two p-type layers, an n-band of n-type silicon is formed so that the transistor can be properly biased. The isolation shown in FIG. 1 is, typically, a shallow trench isolation which is commonly used in semiconductor processes to electrically separate devices.
FIG. 2 shows a top-down physical view of the physical layout of a corner of an embedded DRAM. The contact shown is the bit-line contact. The array well shapes define the boundary of the p-well of the DRAM. The polysilicon gate, along with the bit line contact, controls the access to the charge in the storage capacitor. The n-well shape provides a link to the deep n-type silicon for proper DRAM biasing.
Accordingly, it is an object of the present invention to provide a method for generating a patterned SOI photomask used for embedded DRAMs.
It is another object to provide a method for systematically identifying embedded DRAM areas to be excluded from the SOI process and for generating the shapes to be printed on the photomask so that the eDRAM may be fabricated on bulk silicon.
It is yet another object to provide a method for collecting all the eDRAM array well shapes and all the n-well shapes and respectively merging selected ones of these shapes into single shapes.